Electronic components are typically tested to determine whether they meet various electrostatic discharge (ESD) qualification specifications in order to demonstrate that they will be reliable under ESD conditions to which they may be exposed during manufacturing and handling. ESD exposure may change the electrical characteristics of the components, which may include semiconductor devices, (e.g., integrated circuits (ICs)), that typically have multiple terminals, (e.g., pads, bumps, balls, pins), as well as a package frame or lid, that either directly or indirectly connect to at least one of a power supply, a digital circuit, an analog circuit, or any other external circuit or device.
For an electronic component that resides on, or is cut from, a semiconductor wafer, or is contained in a component package, ESD current may flow between two or more connection points of the electronic component. When the ESD current flows between positive and negative power supply terminals, a supply clamp circuit may be used to dissipate ESD energy directly, thus preventing ESD-induced voltages from damaging the electronic component. A supply clamp circuit typically uses a low-resistance path to shunt ESD current.
When ESD current flows through circuit connections other than the power supply terminals, such as from an input or output (I/O) signal line, it is common practice to divert the ESD current through one or more diodes connected from the I/O signal line to one of the power supply terminals. Upon reaching the power supply, the power supply clamp circuit conducts ESD current through a low-resistance path between the power supply terminals to limit the supply voltage, thus protecting the electronic component from being damaged.
Therefore, supply clamp circuits internal to an electronic component are configured to respond to ESD events and provide a safe path for the dissipation of ESD current. These supply clamp circuits are configured to discriminate between an ESD event, where a clamp transistor is used to provide a low-resistance path to shunt ESD current, and a normal supply powered or ramp-up operation, where the clamp transistor must remain deactivated (i.e., off) and in a low-current state. A supply clamp circuit that employs a function that latches itself into an ESD-event state upon detection of ESD exposure must not be falsely triggered in response to a normal power-on operating condition. Otherwise, the supply clamp circuit may be damaged by the unlimited energy of an active power supply.
In non-latching designs, a resistor-capacitor (RC) circuit may be used to detect an ESD event and activate the clamp transistor to provide a low-resistance supply short to dissipate the ESD energy in a safe manner. In the most classic design, an RC timer remains enabled for the full duration of the ESD event state; (e.g., approximately 2 microseconds). The RC time constant must also be substantially shorter than the time over which a power supply ramps up to its static level in normal operation; (e.g., 10 microseconds or larger).
In configurations of supply clamp circuits that do not latch themselves into a lower resistance state after detecting an ESD event, a very large RC time constant is required, (e.g., 1 to 2 microseconds), to continue clamping until ESD energy is completely dissipated. Supply clamp circuits designed in this manner require an RC circuit that occupies a very large chip (die) area. Such supply clamp circuits are susceptible to failure if the leakage current through the capacitor in the RC circuit is large. In contrast, supply clamp circuits that latch into an ESD-event-detected state can use much smaller RC time constants, since they must only differentiate the rate of the supply ramp between a normal power supply ramp-up operation and an ESD event state. When ESD is discharged through a circuit supply terminal, the ramp rate is generally under 100 nanoseconds, while the rate for a normal power supply ramp-up operation is typically 10 microseconds or larger. An ESD circuit with a latching mechanism needs only to detect the leading edge of the ESD event, after which the circuit latches itself into a state indicating an ESD event has been detected, and clamps for as long as an ESD state persists. Thus, there is no long-duration RC timer expiration that determines ESD event end time. Instead, a loss of latched ESD state, due to a mostly collapsed supply voltage, stops any further clamping from occurring.
The latching mechanism in this modified design is typically formed through a feedback circuit, which maintains the clamp in its low resistance state until the ESD event has been dissipated. The disadvantage of the latching approach is that the supply clamp circuit becomes susceptible to catastrophic damage if it is falsely triggered under normal operating conditions, since the power supply will continue to provide current into the electronic component and the feedback circuit would never allow the clamp transistor to shut off. As a result, the trigger and feedback circuit must be immune to false triggering over a wide range of conditions, including: 1) power supply ramp time and final voltage level; 2) temperature; 3) power supply noise or ripple; 4) device manufacturing tolerances: resistor, capacitor, n-type channel metal-oxide-semiconductor (NMOS) and p-type channel metal-oxide-semiconductor (PMOS) process variations; and 5) aging effects, such as negative or positive bias temperature instability, (negative gate bias voltage temperature instability (NBTI) or positive gate bias voltage temperature instability (PBTI)), which cause a shift in transistor threshold voltage when a non-zero gate voltage occurs over a long time period.
FIGS. 1 and 2 show two examples of conventional electronic component protection power supply clamp circuits that are connected across a power supply used by an electronic component that typically includes a transistor circuit. Multiple instances of these power supply clamp circuits may be used to handle a particular current.
In FIG. 1, a conventional electronic component protection power supply clamp circuit 100 is shown that includes capacitors 102 and 104, a resistor 106, a diode 108, PMOS transistors 110, 112 and 114, and NMOS transistors 116, 118 and 120. Each of these components is connected to at least one of a negative power supply terminal (Vss) 122 or a positive power supply terminal (Vdd) 124. The PMOS transistor 110 includes a gate terminal 126, a source terminal 128 and a drain terminal 130. PMOS transistor 112 includes a gate terminal 132, a source terminal 134 and a drain terminal 136. PMOS transistor 114 includes a gate terminal 138, a source terminal 140 and a drain terminal 142. NMOS transistor 116 includes a gate terminal 144, a source terminal 146 and a drain terminal 148. NMOS transistor 118 includes a gate terminal 150, a source terminal 152 and a drain terminal 154. NMOS transistor 120 serves as a clamp transistor that includes a gate terminal 156, a source terminal 158 and a drain terminal 160. The source terminals 146, 152 and 158 are connected to Vss 122. The source terminals 128, 134 and 140, and the drain terminal 160, are connected to Vdd 124.
As shown in FIG. 1, capacitor 102 is connected between Vdd supply 124 and a node 162. The capacitor 104 is connected between Vdd 124 and a node 164. The resistor 106 is connected between Vss 122 and the node 162. The diode 108 includes an anode 166 that is connected to Vss 122, and a cathode 168 that is connected to Vdd 124. The node 162 is also connected to the gate terminal 132 of the PMOS transistor 112, the gate terminal 144 of the NMOS transistor 116 and the drain terminal 130 of PMOS transistor 110. The node 164 is also connected to the drain terminal 136 of PMOS transistor 112, the drain terminal 148 of NMOS transistor 116, the gate terminal 126 of the PMOS transistor 110, the gate terminal 138 of the PMOS transistor 114, and the gate terminal 150 of NMOS transistor 118. A node 170 connects together the drain terminal 142 of the PMOS transistor 114, the drain terminal 154 of the NMOS transistor 118 and the gate terminal 156 of the NMOS transistor 120.
In the circuit 100 of FIG. 1, a “latch” is essentially formed by two inverters: a first inverter 172 including the transistors 112 and 116, and a second inverter 174 including the transistor 110, which provides inversion for only one polarity. Thus, the inverters 172 and 174 run back-to-back, whereby each inverter 172 and 174 feeds the other's input, thus constituting a latch configuration 172/174. The resistor 106 assures that the voltage input on node 162 starts out by feeding a logic low voltage to the gates 132 and 144 of the inverter 172. As the power supply providing Vss 122 and Vdd 124 ramps up in response to the occurrence of an ESD event, the output of the latch configuration 172/174 (i.e., node 164) serves as latch feedback to cause latching to occur. During an ESD event where the power supply ramps up very rapidly, the capacitor 102 does not develop any significant voltage drop, thus causing a short circuit to form between the power supply and the inverter 172. Thus, an output low on node 164, which turns on the transistor 110 in the inverter 174, causes the voltage across the capacitor 102 to remain substantially at zero, thus latching the ESD event.
In addition, the transistors 114 and 118 form a third inverter 176, which feeds a logic high voltage to the gate 156 of the transistor 120 to clamp, (i.e., short circuit), the power supply in order to keep the Vdd 124 from going too high. The diode 108 deals with ESD current due to reverse supply polarity. For such ESD reverse current, the diode 108 is forward-biased to safely limit the supply voltage.
In FIG. 2, an alternative conventional electronic component protection power supply clamp circuit 200 is shown that includes capacitors 202 and 204, a resistor 206, a diode 208, PMOS transistors 210, 212 and 214, and NMOS transistors 216, 218, 220, 222 and 224. The circuit 200 has transposed the RC circuit formed by the capacitor 202 and the resistor 206 with a corresponding latch inverter as NMOS transistor 216. Operation of the circuit 200 is similar to that of the circuit 100 of FIG. 1, except that the polarity of the RC and feedback stages is reversed. The addition of a third inverter formed by the transistors 214 and 222 may be beneficial in some cases by enabling a reduction in the size of the inverter formed by the transistors 210 and 218, and the feedback transistor 216.
The problem with the circuit 100 of FIG. 1 is that there is no assurance that node 164 will follow the power supply as it ramps up in preparation for normal operation. A normal supply ramp is so slow, (e.g., on the order of 10 microseconds or slower), that the capacitors 102 and 104 may exhibit the characteristics of an open circuit due to the RC time constant of the resistor 106 and the capacitor 102. Thus, node 162 should remain at the Vss 122 potential during a normal power supply ramp-up operation. Although this should cause node 164 to follow Vdd 124 as the power supply voltage rises, a moderate amount of supply noise or transistor imbalance can falsely activate the latch, causing the power supply to be clamped as though it were an ESD event. There is a similar problem with the circuit 200 of FIG. 2, whereby the node 262 remains at the Vdd potential during a normal power supply ramp-up operation.
In both of the conventional circuits 100 and 200, false activation of the clamp circuit in normal operation is destructive to the circuit. Furthermore, since manufacturing thresholds may vary based on operating conditions, the circuits 100 and 200 may fail to power up correctly.